The present invention relates to electrical circuits, and, more particularly, to a binary encoding circuit for the conversion of a plurality of binary input signals into a binary output code and related methods.
According to prior art, binary encoding circuits are realized by combinatorial networks that provide output signals, which constitute the output code, in accordance with the logic levels assumed by the binary signals present at the input. As a general rule, a combinatorial network is implemented from the circuit point of view by logic gates (NOT, AND, OR, etc.) and the design of the network architecture can be obtained by starting from code tables (or from Karnough maps) that express the input-output relationship of the desired encoding circuit.
However, these conventional design techniques do not make it possible to obtain combinatorial networks and, more particularly, encoding circuits that employ a reduced or minimal number of logic gates and are characterized by a simple architecture.
The reduction or minimization of the number of logic gates and the complexity of the architecture of the combinatorial encoding network is particularly critical when the network is to be realized with integrated semiconductor circuits. In this connection it should be noted, for example, that when CMOS (Complementary Metal-Oxide Semiconductor) technology is used, a single NAND logic gate is realized by two PMOS transistors and two NMOS transistors.
Furthermore, it should be noted that the conventional encoding circuits permit the assertion (or activation) of only a single input line at a time, i.e. only a single input line is asserted in each specific operating condition. For example, a decoding circuit (which has a structure that corresponds to that of an encoding circuit) employed for processing row address codes of memory cell matrices in FAMOS (Floating-gate Avalanche MOS) technology will permit the assertion of only a single output line, a word-line of the memory matrix, in each specific operating condition. According to the prior art, moreover, this limitation can be overcome only by realizing encoding circuits with priority, i.e. circuits for which not all the input signals have the same weight in the subsequent encoding process.
It has been noted that there can be applications of encoding circuits for which the possibility offered by conventional encoding circuits of either activating only a single output line in each specific operating condition, or introducing a priority ranking among the input signals, can constitute an unacceptable limitation.
In view of the foregoing background, it is therefore an object of the present invention to provide an encoding circuit that will make it possible to overcome the limitations and drawbacks associated with the prior art techniques.
This and other objects of the invention are provided by a binary encoding circuit for converting a plurality of binary input signals, including at least first and second input signals, into an output code including at least first and second binary output signals. The circuit may comprise at least two logic value supply terminals to render available a signal of a high logic level and a signal of a low logic level. The circuit may also include at least one first selection circuit comprising first and second output lines capable of being selectively connected to the logic value supply terminals based upon a logic level of the first input signal. In addition, the encoding circuit may also include at least one second selection circuit comprising third and fourth output lines capable of being selectively connected to at least one of the first and second output lines based upon a logic level of the second binary input signal. The first and second binary output signals may be provided by signals available on the third and fourth output lines.